1. Field of the Invention
This invention relates to an EL (electro-luminescence) display device formed by constructing a semiconductor device (i.e., a device made of a semiconductor thin film) on a substrate and relates to electronic equipment (electronic device) in which the EL display device is used as a display panel (display portion).
2. Description of Related Art
In recent years, great advances have been made in a technique for forming TFTs on a substrate, and development has proceeded in the application thereof to an active matrix type display. Especially, a TFT using a polysilicon film is higher in electron field-effect mobility than a conventional TFT using an amorphous silicon film, and can operate at a high speed. Therefore, it has been made possible to control a pixel by a driving circuit formed on the same substrate on which the pixel is also formed, although the pixel had been conventionally controlled by the driving circuit disposed outside the substrate.
The active matrix type display is attracting public attention because it can obtain various advantages, such as reduced manufacturing costs, reduced size of the display device, increased yields, and reduced throughput, by constructing various circuits or elements on the same substrate.
Conventionally, the pixel of the active matrix type EL display has been generally constructed as shown in FIG. 3. In FIG. 3, reference character 301 designates a TFT that functions as a switching element (hereinafter, referred to as switching TFT), 302 designates a TFT that functions as an element (current controlling element) to control a current supplied to an EL element 303 (hereinafter, referred to as current controlling TFT), and 304 designates a capacitor (capacitance storage). The switching TFT 301 is connected to a gate wiring line 305 and a source wiring line 306 (data wiring line). The drain of the current controlling TFT 302 is connected to the EL element 303, and the source thereof is connected to a current-feed line 307.
When the gate wiring line 305 is selected, the gate of the switching TFT 301 is opened, the data signal of the source wiring line 306 is then stored in the capacitor 304, and the gate of the current controlling TFT 302 is opened. After the gate of the switching TFT 301 is closed, the gate of the current controlling TFT 302 is kept opening by the charge stored in the capacitor 304. During that interval, the EL element 303 emits light. The amount of luminescence of the EL element 303 changes according to the amount of a flowing current.
At this time, the amount of current supplied to the EL element 303 is controlled by the gate voltage of the current controlling TFT 302. This is shown in FIG. 4.
FIG. 4(A) is a graph showing transistor characteristics of the current controlling TFT. Reference character 401 is called Id-Vg characteristic (or Id-Vg curve). Herein, Id is a drain current, and Vg is a gate voltage. The amount of a flowing current corresponding to an arbitrary gate voltage can be known from this graph.
Normally, the region shown by the dotted line 402 of the Id-Vg characteristic is used when the EL element is driven. An enlarged view of the enclosed region of the dotted line 402 is shown in FIG. 4(B).
In FIG. 4(B), the region shown by the oblique lines is called a sub-threshold region. In practice, it is indicated as a region in which a gate voltage is near or less than a threshold voltage (Vth). The drain current exponentially changes according to the change of the gate voltage in this region. Using this region, the current is controlled by the gate voltage.
The data signal input into a pixel by opening the switching TFT 301 is first stored in the capacitor 304, and the data signal directly acts as the gate voltage of the current controlling TFT 302. At this time, the drain current with respect to the gate voltage is determined by one-to-one according to the Id-Vg characteristic shown in FIG. 4(A). That is, a given current flows through the EL element 303 corresponding to the data signal, and the EL element 303 emits light by the amount of luminescence corresponding to the amount of the current.
The amount of luminescence of the EL element is controlled by the data signal, as mentioned above, and thereby gradation display is performed. This is a so-called analog gradation method, in which the gradation display is performed by a change in the amplitude of the signal.
However, there is a defect in that the analog gradation method is very weak in the characteristic variability of TFTs. For example, let it be assumed that the Id-Vg characteristic of a switching TFT differs from that of a switching TFT of an adjacent pixel that displays the same gradation level (i.e., a shift is performed toward a plus or a minus side overall).
In this situation, drain currents of the switching TFTs differ from each other, though depending on the level of the variability, and thus a different gate voltage will be applied to the current controlling TFT of each pixel. In other words, a different current flows through each EL element, and, as a result, a different amount of luminescence is emitted, and the display of the same gradation level cannot be achieved.
Additionally, even if an equal gate voltage is applied to the current controlling TFT of each pixel, the same drain current cannot be output if the Id-Vg characteristic of the current controlling TFTs has variability. Additionally, as is clear from FIG. 4(A), a region is used in which the drain current exponentially changes according to a change in the gate voltage, and, therefore, a situation will occur in which, if the Id-Vg characteristic shifts most slightly, the amount of current to be output becomes greatly different even if an equal gate voltage is applied thereto. If so, adjacent pixels will have a great difference in the amount of luminescence of the EL element.
In practice, each individual variability of the switching TFT and the current controlling TFT acts synergistically, and a stricter condition will be imposed. The analog gradation method is extremely sensitive to the characteristic variability of the TFTs, as mentioned above, and this has caused an obstruction to realizing the multicolor of the conventional active matrix type EL display device.
The present invention was made in consideration of the above problem, and it is an object of the present invention to provide an active matrix type EL display device capable of performing clear multi-gradation color display. It is another object of the present invention to provide high-performance electronic equipment provided a with such an active matrix type EL display device.
The present applicant thought that a digital gradation method in which the current controlling TFT is used only as a switching element for supplying a current is better than the conventional analog gradation method in which the amount of luminescence of the EL element is controlled by controlling a current, in order to design a pixel structure to be unsusceptible to the influence of the characteristic variability of the TFT.
From this, the present applicant thought that the most desirable gradation display method in the active matrix type EL display device is a divided gradation display method, more specifically, a gradation display method under a time-division method (hereinafter, designated as time-division gradation or time-division gradation display).
In practice, the time-division gradation display is performed as follows. A description is herein given of a case in which the full color display of 256-gradation (16,770,000 colors) is performed according to an 8-bit digital driving method.
First of all, one frame of an image is divided into eight sub-frames. Herein, one cycle when data is input to all pixels of a displayed area is called one frame. Oscillation frequency in a normal EL display device is 60 Hz, in other words, 60 frames are formed per second. Flickering of the image, for example, begins to be visually conspicuous when the number of frames per second falls below this. A divided frame obtained by dividing one frame into a plurality of frames is called a sub-frame.
One sub-frame is divided into an address period (Ta) and a sustained period (Ts). The address period is the entire time required to input data to all pixels during one sub-frame, and the sustained period (or lighting period) is a period during which the EL element emits light. (FIG. 10).
Herein, the first sub-frame is called SF1, and the remaining sub-frames from the second to the eighth sub-frame are called SF2-SF8, respectively. The address period (Ta) is constant in SF1-SF8. On the other hand, the sustained periods (Ts) corresponding to SF1-SF8 are called Ts1-Ts8, respectively.
At this time, the sustained periods are arranged to be Ts1:Ts2:Ts3:Ts4:Ts5:Ts6:Ts7:Ts8=1:1/2:1/4:1/8:1/16:1/32:1/64:1/128. However, the order in which SF1-SF8 are caused to appear does not matter. Desired gradation display among 256 gradations can be performed by combining the sustained periods.
First of all, in a state in which a voltage is not applied (or not selected) to an opposite electrode of an EL element of a pixel (note that the opposite electrode is an electrode not connected to a TFT; normally, this is a cathode), a data signal is input to each pixel without light emission of the EL element. This period is defined as an address period. When the data is input to all the pixels and the address period is completed, a voltage is applied (or selected) to the opposite electrode, thus allowing the EL element to emit light. This period is defined as a sustained period. The period during which light is emitted (i.e., the pixel is lit) is any one of Ts1-Ts8. Let it be herein supposed that a predetermined pixel is lit during Ts8.
Thereafter, taking again an address period, a data signal is input to all pixels, and then a sustained period is entered. At this time, the sustained period is any one of Ts1-Ts7. Let it be herein supposed that a predetermined pixel is lit during Ts7.
Thereafter, the same operation is repeated for the remaining six sub-frames, and, by setting the sequential sustained periods in the order of Ts6, Ts5, . . . and Ts1, a predetermined pixel is lit in each sub-frame.
When eight sub-frames appear, one frame is finished. At this time, the gradation of the pixel is controlled by multiplying the sustained periods. For example, when Ts1 and Ts2 are selected, a brightness of 75% can be expressed on the supposition that all the light is 100%, and, when Ts3, Ts5, and Ts8 are selected, a brightness of 16% can be expressed.
256-gradation display was described above, but other gradation display can be performed.
When the gradation display (2n-gradation display) of n bit (n is an integer of two or more) is performed, one frame is first divided into n sub-frames (SF1, SF2, SF3, . . . SF(nxe2x88x921), and SF(n)), while corresponding to the gradation of n bit. The number of divisions of one frame increases as the gradation increases, and a driving circuit must be operated at a high frequency.
The n sub-frames are each divided into address periods (Ta) and sustained periods (Ts). In other words, the address and sustained periods are selected by selecting whether to apply a voltage to an opposite electrode common to all EL elements or not.
And, the sustained period corresponding to each of the n sub-frames is processed to be Ts1:Ts2:Ts3: . . . :Ts(nxe2x88x921):Ts(n)=20:2xe2x88x921:2xe2x88x922: . . . :2xe2x88x92(nxe2x88x922):2xe2x88x92(nxe2x88x921) (herein, the sustained period corresponding to SF1, SF2, SF3, . . . , SF(nxe2x88x921), and SF(n) is Ts1, Ts2, Ts3, . . . , Ts(nxe2x88x921), and Ts(n), respectively).
In this state, a pixel is sequentially selected in one arbitrary frame (more strictly, the switching TFT of each pixel is selected), and a predetermined gate voltage (corresponding to a data signal) is applied to the gate electrode of the current controlling TFT. At this time, the EL element of a pixel to which the data signal actuating the current controlling TFT is input emits light only during the sustained period allocated to the sub-frame after completion of the address period. That is, a predetermined pixel emits light.
This operation is repeated in all the n sub-frames, and the gradation of each pixel is controlled by multiplying the sustained periods. Accordingly, when paying attention to an arbitrary pixel, the gradation of the pixel is controlled according to how long the pixel is lit in each sub-frame (i.e., how long the sustained period has lasted).
As mentioned above, it is the most noticeable feature of the present invention that time-division gradation display is used for the active matrix type EL display device. In order to perform this time-division gradation, one frame must be divided into a plurality of sub-frames. In other words, it is more necessary than before to improve the operating frequency of the driving circuits on the data signal side and on the gate signal side.
However, it is difficult to make a TFT capable of operating at such a high speed from the conventional polysilicon film (also called a polycrystal silicon film). The operation frequency can be decreased by dividing the driving circuit on the data signal side into a plurality of circuits, but a satisfactory result cannot be accomplished if so.
Therefore, in the present invention, use is made of a silicon film having a peculiar crystal structure in which the continuity of a grain boundary is high and the crystal orientation is unidirectional. This film is used as an active layer of a TFT, thereby allowing the TFT to exhibit very high operation and speed. That is, it is one of the features of the present invention to also perform the time-division gradation display of the active matrix type EL display device by the use of such a high operating speed TFT. A description is hereinafter given of observed results of a silicon film used in the present invention that was made experimentally.
The silicon film used in the present invention has a crystal structure in which, microscopically, a plurality of needle-shaped crystals or bar-shaped crystals (hereinafter, designated as bar crystal) gather and form lines. This can be easily confirmed from observations according to the TEM (transmission electron microscope).
Additionally, as a result of carrying out detailed observations of an electron beam diffraction image of a spot diameter of about 1.35 xcexcm concerning the silicon film used in the present invention, diffraction spots corresponding to a {110} plane appear regularly in spite of the existence of a slight fluctuation, and it can be confirmed to have the {110} plane as a main orientation plane though a crystallographic axis has a slight deviation.
FIG. 19(A) shows an electron beam diffraction image obtained by projecting an electron beam of a spot diameter of about 1.35 xcexcm onto the silicon film used in the present invention. On the other hand, FIG. 19(B) shows an electron beam diffraction image obtained by projecting an electron beam onto the conventional polysilicon film under the same conditions. In each figure, the center of the photograph is a position (projected point of the electron beam) onto which the electron beam was projected.
While the diffraction spots corresponding to the {110} plane appear comparatively regularly in FIG. 19(A), they are arranged to be quite irregular in FIG. 19(B), and thus the orientation planes are obviously nonuniform. From this electron beam diffraction photograph, the silicon film used in the present invention can be immediately distinguished from the conventional polysilicon film.
In the electron beam diffraction image of FIG. 19(A), it is obvious, by comparison with the electron beam diffraction image of a monocrystal silicon wafer of the {110} orientation, that the diffraction spot corresponding to the {110} plane appears. Additionally, while the diffraction spot of the monocrystal silicon wafer is seen as a sharp spot, the diffraction spot of the silicon film used in the present invention has an expanse on the concentric circle centering the projected point of the electron beam.
This is also a feature of the silicon film used in the present invention. Since the {110} plane is an individual orientation plane for each crystal grain, it is expected that the same diffraction spot as the monocrystal silicon is obtained as far as one crystal grain is concerned. However, in practice, they exist as a collective of a plurality of crystal grains, and therefore each grain has a slight rotation around the crystallographic axis, and a plurality of diffraction points, each corresponding to the crystal grain appear on the concentric circle, though each crystal grain sets the {110} plane as its own orientation plane. The points are laid upon each other so as to exhibit an expanse.
However, since an each individual crystal grain forms a grain boundary quite excellent in consistency, as described later, the slight rotation around the crystallographic axis does not constitute a factor for ruining crystallinity. Therefore, it can be said that the electron beam diffraction image of the silicon film used in the present invention substantially has no distinction to the electron beam diffraction image of the monocrystal silicon wafer of the {110} orientation.
From the foregoing, it may safely be affirmed that the silicon film used as an active layer of a TFT in the present invention is the silicon film showing the electron beam diffraction image corresponding to the {110} orientation.
Now, a description will be given of the grain boundary of the silicon film used in the present invention. Although a description is given under the designation of xe2x80x9cgrain boundaryxe2x80x9d for convenience of explanation, this can be regarded as an interface between a certain crystal grain and another crystal grain that has derived (or branched) therefrom. Anyway, the designation of xe2x80x9cgrain boundaryxe2x80x9d including the meaning of the aforementioned interface is used in this specification.
The present applicant confirmed that, from observation of a grain boundary formed by the contact of individual bar crystals under the HR-TEM (high-resolution transmission electron microscope), there is continuity in the crystal lattice in the grain boundary. This can be easily confirmed from the fact that lattice fringes under observation are continuously linked to each other in the grain boundary.
The continuity of the crystal lattice in the grain boundary originates from the fact that it is a grain boundary called xe2x80x9cplanar boundaryxe2x80x9d. The definition of the planar boundary in this specification derives from xe2x80x9cPlanar Boundaryxe2x80x9d appearing in xe2x80x9cCharacterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol. 27, No. 5, pp. 751-758, 1988.xe2x80x9d
According to the above article, the planar boundary includes a twin grain boundary, a special lamination fault, and a special twist grain boundary. This planar boundary has a feature in that it is electrically inert. That is, although it is a grain boundary since the planar boundary does not function as a trap to obstruct the movement of a carrier, it can in fact be considered as no existence.
Especially, when the crystallographic axis (axis perpendicular to the crystal plane) is the  less than 110 greater than  axis, the {211} twin grain boundary and the {111} twin grain boundary are often called a corresponding grain boundary of xcexa33. A xcexa3 value is a parameter serving as an indicator that shows the level of the consistency of the corresponding grain boundary, and it is known that the grain boundary increases in excellence in consistency as the xcexa3 value falls.
As a result of observing the silicon film used in the present invention by the TEM, almost all the grain boundaries have proved to be corresponding grain boundaries of xcexa33. This was judged from the fact that a grain boundary formed between two crystal grains becomes the corresponding grain boundary of xcexa33 when xcex8=70.5xc2x0 wherein xcex8 is an angle formed by the lattice fringes corresponding to the {111} plane when the plane orientation of both crystal grains is {110}.
It is noted that it becomes the corresponding grain boundary of xcexa39 when xcex8=38.9xc2x0, and other grain boundaries, such as this grain boundary, also exist.
The crystal structure (more accurately, structure of the grain boundary) shows that two crystal grains different in the grain boundary are connected to each other with quite excellently consistency. In other words, a structure is established in which crystal lattices range continuously in the grain boundary, and it is very difficult to create a trap level resulting from, for example, a crystal fault. Therefore, a semiconductor thin film that has a crystal structure such as the above one can in fact be considered to have no grain boundary.
It is confirmed by TEM observation that faults (stacking fault etc.) existing in the crystal grain disappear almost completely by conducting a heating process at 700-1150xc2x0 C. in sequential steps when the silicon film used in the present invention is formed. This is apparent from the fact that the number of faults is greatly decreased before and after the heating process.
The difference in the number of faults appears as the difference in the spin density according to electron spin resonance analysis (ESR analysis). In the current state, the spin density of the silicon film used in the present invention has proved to be at least 5xc3x971017 spins/cm3 or less (preferably, 3xc3x971017 spins/cm3 or less). However, since this measurement value is close to the detection limit of measuring devices in existence, it is expected that an actual spin density is even lower.
A further detailed description of the silicon film used in the present invention can be supplied by Patent Application Nos. 044659 of 1998, 152316 of 1998, 152308 of 1998, and 152305 of 1998, each filed by the present applicant.
A TFT in which the silicon film used in the present invention is experimentally made an active layer shows an electrical characteristic that equals MOSFET. The following data are obtained from the TFT (in which the film thickness of the active layer is 30 nm, and that of the gate insulating film is 100 nm) experimentally made by the present applicant.
(1) The sub-threshold coefficient which is the index of switching performance (quickness of on/off operation switch) is 60xcx9c100 mV/decade (representatively, 60xcx9c85 mV/decade) in both N-channel type TFT and P-channel type TFT: this value is small.
(2) The electron field-effect mobility (xcexcFE) which is the index of the operation speed of the TFT is 200xcx9c650 cm2/Vs (300xcx9c500 cm2/Vs representatively) in N-channel type TFT, and is 100xcx9c300 cm2/Vs (150xcx9c200 cm2/Vs representatively) in P-channel type TFT: these values are large.
(3) The threshold voltage (Vth) which is the index of the driving voltage of the TFT is xe2x88x920.5xcx9c1.5 in N-channel type TFT, and is xe2x88x921.5xcx9c0.5 in P-channel type TFT: these values are small.
It is confirmed to be capable of realizing quite excellent switching characteristics and high-speed operation properties, as described above. In addition, in a ring oscillator experimentally made by the use of the TFT, the oscillation frequency of about 1 GHz is obtained at the maximum. The ring oscillator is constructed as follows.
Number of steps: nine steps;
Film thickness of the gate insulating film of the TFT: 30 nm and 50 nm;
Gate length of the TFT (channel-length): 0.6 xcexcm.
Additionally, as a result of actually making a shift register experimentally and confirming the operation frequency, the output pulse of the operation frequency of 100 MHz is obtained in the shift register in which the film thickness of the gate insulating film is 30 nm, the gate length is 0.6 xcexcm, the power supply voltage is 5V, and the number of steps is 50.
The marvelous data of the ring oscillator and the shift register mentioned above indicate that the TFT in which the silicon film used in the present invention is made an active layer equals MOSFET, which uses a monocrystal silicon, or has operational performance surpassing MOSFET.